• A hardware-enhanced software isolation solution that enable Trusted Execution Environments (TEEs) on RISC-V by SiFive.
• Design verification of the WorldGuard Security from unit testbences to the CoreIP system.
• Developing and maintaining the software model of WorldGuard for the Spike simulator.

• TileLink is a new coherent bus protocol introduced by SiFive to the RISC-V ecosystem. 
• Involved in developing the verification infrastructure for the latest versions of the TileLink protocol. 
• Assertions and coverpoints of different levels of complexities were implemented during the project aiming a total verification at the protocol level.
• Development done using Chisel which is Scala Embedded HDL.

• Software for verification of VLSI designs
• Utilizing cutting-edge simulators and programming languages
• Software modeling of digital and analog hardware components
• Accurate simulations of both individual components and entire SoCs
• Creating custom simulators to meet specific SoC requirements
• By a team of engineers with expertise in software and electronics

• Experienced in software support for new SoC bring-ups.
• Specialize in PCIe driver development.
• Conduct Wafersort testing and characterization.
• Expertise in test board bring-up processes.
• Skilled team with experience in various SoC types, including Analog-Digital hybrids.
• Extensive work in characterization for optimum trims in complex systems.

• Proficient in developing comprehensive regression suites.
• Implement test automation solutions for hardware and software reliability.
• Use advanced tools for meticulous test design and execution.
• Employ shell and Python scripting for efficient test process automation.
• Integrate with Jenkins for regular test runs and continuous system monitoring.
• Automation expedites testing, ensuring consistent and accurate assessments.
• Provide detailed regression reports for insights into product stability and evolution.

• An FPGA-based SDI video acquisition and playback system built on a Xilinx Zynq UltraScale+ platform, supporting SD to 12G SDI standards. The system captures SDI video streams, transfers data to a host system via PCIe for further processing or storage, and performs real-time, custom video processing within the FPGA. Processed or host-provided video is then transmitted back through the SDI interface for playback, enabling a complete end-to-end video pipeline.

• HDMI video passthrough system with a real time video processing of Histogram Equalization implemented on Zynq Ultrascale+ MPSoC SOM(TE0807) pluggable custom carrier board. Designed the Histogram Equalization IP using High Level Synthesis tool. The
  system supports all the standard video formats, the maximum resolutions and frame rates up to 4k and 60Hz. The system is auto configurable and there is no need to configure the format of the video input before its video process. SoC runs the application that controls all the functions and transmit out the system log (video resolution, frame rates and HDMI Tx Rx reference clocks) to the PC via UART.

• HEVC video decoder IP core by Paraqum Technologies is an all-hardware, high performance video decoder which is easily integrable to complex FPGA based SoCs and supports upto 4K video decoding at 30 fps on Xilinx 7 series FPGAs.
• The core architecture is optimized for very low resource utilization. Coupled with low running frequencies (150 MHz), Paraqum HEVC Decoder IP core is ideal for deployment in mid-range FPGAs.
• The decoder complies with H.265 main profile level 5 and supports output bitrates up to 4K@30 fps or 1080p@120 fps while the max input bit rate is 20 Mbps.
• The output is having YUV colour format and supports 4:2:0, 4:2:2 and 4:4:4 chroma formats. It can be configured to run on pixel bit depths of 8, 10 or 12.

• HEVC video encoder IP core is an all-hardware, high performance, low frequency design readily deployable in Xilinx 7 Series FPGAs.
• It comes with well defined AXI interfaces for the integration with complex FPGA or SoC deisgns to encode full HD (1920x1080) video complying the H.265 standard.
• The encoding includes the highly computationally intensive operations such as intra prediction, inter prediction, transform, split handling, etc. all performed in hardware.
• The encoder takes YUV input with 4:2:0, 4:2:2 and 4:4:4 chroma formats up to 1080p@60 fps and can be configured to pixel bit depths of 8, 10 or 12.

• Object detection
• Image recognition
• Facial recognition systems
• Augmented reality applications
• Utilizing state-of-the-art algorithms like convolutional neural networks (CNN) and deep learning architectures
• Applied in autonomous driving, security surveillance and entertainment industry

• Sentiment analysis
• Named entity recognition
• Language translation
• Chatbot development
• Tailored NLP solutions to meet industry needs
• Enabling businesses to automate processes and improve customer interactions

A series of equipment related to video broadcasting industry was done for a USA based customer. Product series includes

• Video Format converters
• Video Capture Cards
• Video switches, distribution amplifiers

• Artix and Zynq ICs on a single board​
• DDR4 Memory, 10G SFP+, HDMI, SDI​
• 16-layer HDI PCB with buried/blind vias 

• 14-layer PCB
• Layout for DDR4 memory
• 4x 10Gbps data rate

• 4x 4K SDI video processing board
• Supports Trenz UltraSOM Zync UltraScale+ FPGA board​
• Compact design​
• Supports 12Gbps data rate 
• Multi IO FPGA Carrier Board​ 
  
• Support 2 units of Trenz UltraSOM boards​ 
  
• On board peripherals (USB-C, HDMI 4K, SDI 12G, Display Port, 10G Ethernet, Analog Video in, WiFi)
  

• Refrigerator controller board
• Washing machine controller board
• Capacitive touch user interfacing​
• Low margin high volume product​ 
• Building automation system GUI
• Developing graphical user interfaces using emWin - Industry Leading Embedded Graphics Library​
• The client wanted to have android like graphical user interface on its old hardware.